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A function generator produces waveforms at user-selected frequencies. You will design and implement an FPGA based function generator that supports frequencies from 10Hz to 10kHz

ELEE1156 Hardware Systems and Control Coursework Assignment

1. Introduction

Through lab exercises and lectures, you have gained experience in implementing VHDL designs using various techniques. You will now apply these skills to design and build a function generator.

This project will allow you to demonstrate your abilities in VHDL design hardware interfacing, and simulation.

2. Assignment

A function generator produces waveforms at user-selected frequencies. You will design and implement an FPGA based function generator that supports frequencies from 10Hz to 10kHz and offers the following waveform options:

  • PWM waveform with adjustable duty cycle
  • Sine waveform

Design the function generator using VHDL and implement it on the DE1-SoC development board, using the board`s buttons, switches, LEDs, and seven-segment displays to create a user-friendly interface. 

2.1 Simulation

Simulation of the system can be done using ModelSim (or Questa). Relevant simulation should include verification of waveform generation.

2.2 Hardware implementation

Implement the system in hardware and use the DE1-SoC board`s LEDs and/or seven segment displays to visually indicate the output. FPGA output can be connected to the Texas Instruments TLC7524CN DAC to generate an analogue signal for devices like oscilloscopes or speakers.

2.3 Report

You should produce a report (maximum 1500 words, excluding appendices), in pdf format, that gives a comprehensive account of the design process including the hardware setup, VHDL code development, testing and evaluation.

A recommended structure for the report includes the following main headings, with subheadings added as appropriate:

  • Introduction
  • Design methodology
  • VHDL development
  • Testing and Results
  • Evaluation and reflection
  • Conclusion

VHDL code must be appropriately commented and developed using an appropriate design technique (block diagrams, state machine diagrams etc. as appropriate). 

Full listings of the VHDL files that you developed should be included in an appendix, although code excerpts may also be used in the main body of the report to illustrate a particular point.  Listings of VHDL code for any external IP blocks that are used do not have to be included in the report.

Relevant references should be included where appropriate.

3. Assessment

The report must be uploaded to Moodle, in pdf format, using the upload link provided in the ‘Coursework Briefing, Guidance and Submission’.  The report must be uploaded by the due date, which can be seen by clicking the upload link.

This assignment is a summative assessment and contributes 40% to your final module grade.

You can view the assessment rubric by clicking the assignment upload link on the module`s Moodle page.

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About ELEE1156 Hardware Systems and Control Coursework

The ELEE1156 Hardware Systems and Control coursework asks students to design and build a small function generator using VHDL on the DE1-SoC FPGA board. The task is to produce PWM and sine waveforms over a range of 10 Hz to 10 kHz, using the board’s switches, buttons, LEDs and seven-segment displays to control and show the settings. Students must first simulate their design in ModelSim or Questa to check that the waveforms and control logic behave as expected, and then implement and test the circuit in hardware using the TLC7524CN DAC and basic lab equipment. Finally, they write a structured report explaining their design choices, VHDL development, testing process and results, as well as reflecting on what worked well and what could be improved.

Sample Answer

Introduction

This coursework project focuses on designing and implementing a simple function generator on an FPGA. The aim is to produce digital waveforms with user-selected frequency and type, and then convert them to an analogue signal using an external DAC.

The function generator supports frequencies from 10 Hz to 10 kHz and offers two waveform options: a PWM waveform with adjustable duty cycle and a sine waveform. The design is implemented on the DE1-SoC development board. The on-board buttons, switches, LEDs and seven-segment displays are used to provide a basic but clear user interface.

The project covers the full design flow for digital hardware: planning the architecture, writing and simulating VHDL, implementing the design on the FPGA, and testing the system using the Texas Instruments TLC7524CN DAC and lab equipment such as oscilloscopes. The report describes the design process, shows how the VHDL was developed and tested, and reflects on the performance and limitations of the final system.

Design Methodology

The first step was to decide how to generate waveforms digitally over the required frequency range. For the sine wave, a common method is to store one period of the sine curve in a lookup table and step through it at the correct speed. For the PWM waveform, the simplest method is to use a counter and a comparator to control the duty cycle.

A top-level block diagram was sketched to identify the main parts of the system:

  • Clock and timing block – derives timing signals and phase updates from the main FPGA clock.

  • Sine generator – uses a phase accumulator and a ROM table of sine samples.

  • PWM generator – uses a counter and a duty cycle register.

  • User interface – reads switches and buttons and drives LEDs and seven-segment displays.

  • DAC interface – sends digital sample values to the TLC7524CN.

The DE1-SoC board provides a stable high-frequency clock, typically 50 MHz. From this, the design derives the lower frequencies for the waveforms. A numerically controlled oscillator (NCO) style phase accumulator was used for the sine wave. The phase accumulator adds a fixed step value on every clock cycle; the upper bits of the accumulator act as an address into the sine table. A larger phase step produces a higher output frequency.

The 10 Hz to 10 kHz range is wide, so the frequency selection was divided into ranges controlled by switches. For example, one range can cover tens of hertz, another hundreds, and another thousands. Push-buttons allow the user to move up or down through a small set of predefined frequencies within each range. This approach keeps the logic simple but still demonstrates control over a wide frequency span.

For the PWM waveform, a free-running counter increments from zero to a set maximum and then restarts. The duty cycle is controlled by comparing the counter value to a duty register. When the counter is less than the duty value, the output is high; otherwise it is low. Buttons are used to increase or decrease the duty value in fixed steps, giving a small set of useful duty cycles such as 25%, 50% and 75%.

The user interface design aimed to make good use of the DE1-SoC board hardware without becoming over-complicated. One switch selects between sine and PWM modes, another selects frequency range, LEDs indicate the active waveform, and the seven-segment displays show the approximate output frequency or duty cycle.

Checking you have met the brief

Before you finish, confirm:

  • PWM waveform implemented with adjustable duty cycle.

  • Sine waveform implemented via LUT/ROM.

  • Frequency range covers 10 Hz to 10 kHz.

  • User interface uses buttons, switches, LEDs, seven-segment displays.

  • Simulation in ModelSim/Questa includes waveform verification.

  • Hardware test done on DE1-SoC and DAC used to create analogue output.

  • Report has the required headings and is under 1500 words (excluding appendices).

  • VHDL listings included in appendix, with comments.

  • You referenced any datasheets or textbooks you used.

You have to build a small function generator on the DE1-SoC that makes PWM and sine waves from about 10 Hz to 10 kHz using VHDL.

Yes. You first test your design in ModelSim/Questa, then run it on the DE1-SoC board and check the output through the DAC.

You explain your design, show key results from simulation and hardware tests, and then reflect on what worked well and what you would improve.

It’s important because it turns your digital output into a real analogue signal, so you can see your waveform properly on an oscilloscope or hear it on a speaker.

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